Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat
Gujarat - Surat, Gujarat
Vacancies
1
Salary
Research Associate-I (RA-I): Rs. 58,000/- per month + 20% HRA | Project Associate-I (PA-I): Rs. 31,000/- per month + 20% HRA
Last Date
18 Aug 2026
Exam Date
19 Aug 2026
⚠ Please verify all details (dates, eligibility, vacancies) from the official notification before applying. Rojgarpulse is an information aggregator and not a government body.
No application fee
Maximum Age
35 Years
Age relaxation applicable as per govt rules for SC/ST/OBC/PwD/Ex-Servicemen.
Research Associate-I (RA-I): Rs. 58,000/- per month + 20% HRA | Project Associate-I (PA-I): Rs. 31,000/- per month + 20% HRA
Upper Age Limit: 35 years for both posts.
Minimum aggregate First Class / CGPA 6.5 for all qualified degrees. Candidates with relevant experience will be given preference.
Research Associate-I (RA-I): Ph.D. in Electronics Engineering or equivalent; OR 3 years of research/teaching/design & development experience after M.E./M.Tech in VLSI Design / Microelectronics / Microelectronics and VLSI Design / Electronics & Communication or equivalent, with at least one research paper in an SCI journal.
Project Associate-I (PA-I): M.E./M.Tech in VLSI Design / Microelectronics / Microelectronics and VLSI Design / Electronics & Communication or equivalent.
Department: Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat
Advertisement No: DECE/ISRO/2025-26 dated 12 August 2026
Project: Algorithm Development For Detection of Spoofing Signals in NavIC Receivers (FPGA-Based)
Funding Agency: RESPOND, ISRO
Last Date: 18 August 2026
Mode of Application: Offline (by Email)
Interview Date: 19 August 2026
Official Website: https://www.svnit.ac.in
| Post | No. of Posts | Consolidated Pay |
|---|---|---|
| Research Associate-I (RA-I) | 01 | Rs. 58,000/- p.m. + 20% HRA |
| Project Associate-I (PA-I) | 01 (combined with RA-I) | Rs. 31,000/- p.m. + 20% HRA |
| Total | 01 |
* Total vacancy is 01. Candidate will be offered either RA-I or PA-I based on qualification.
03 Years or till the completion of the project, whichever is earlier. Initial appointment is for one year, extendable by 2 more years on an annual basis, subject to satisfactory performance and extension of the project.
Upper Age Limit: 35 years for both Research Associate-I and Project Associate-I.
Essential Qualification:
Mandatory Aggregate: Candidates must have a minimum aggregate First Class / CGPA 6.5 for all qualified degrees (B.E./B.Tech/ M.E./M.Tech./M.Sc./Ph.D.). Candidates with relevant experience will be given preference.
Desired Skills: FPGA design and development, VHDL/Verilog Programming; Software Skills - Xilinx Vivado, MATLAB, C/C++, Python; basic GNSS receiver, signal processing, embedded computing, communication systems.
| Event | Date |
|---|---|
| Notification Date | 12 August 2026 |
| Last Date to Apply (by Email) | 18 August 2026 |
| Date of Interview | 19 August 2026 |
Shortlisting of applications followed by Interview.
No application fee for any category.
Interested candidates must submit a duly filled and signed application form along with self-attested scanned copies of B.E./B.Tech/M.E./M.Tech/M.Sc./Ph.D. mark-sheets of all semesters, relevant experience certificates and other necessary documents, as a single PDF file by email to snshah@eced.svnit.ac.in on or before 18 August 2026. Applications received after the said date will not be considered. Candidates must bring the original and Xerox copies of relevant documents at the time of the interview.
Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat, Gujarat. Email: director@svnit.ac.in, hod@eced.svnit.ac.in. Website: https://www.svnit.ac.in
This information is compiled from the official SVNIT advertisement (Advt No. DECE/ISRO/2025-26 dated 12 August 2026). Candidates are advised to verify all details from the official notification before applying.